The distance between plated holes of different nets is dictated by annular rings and trace/space. The tolerance for the other hole sizes are +/-0.003”. Holes 0.014” or smaller may be filled with solder and can only be used as via. These sizes are the finished hole diameters after plating. Limit number of holes to less than 50 per square inch. All holes with copper pads on the top and bottom are plated through, while holes without a copper pad on the top or bottom layer are non-plated.Īll hole sizes between and including 0.010” and 0.247” are available, up to tolerance. All holes with copper pads on the top and bottom are plated through, while holes without a copper pad on the top or bottom layer are non-plated.Ĥ-Layer / 6-Layer Design: Boards are manufactured with 4 (or 6) copper layers. Calculate annular ring by subtracting the diameter of the via hole from the diameter of the via pad and dividing by two.Ģ-Layer Design: Boards are manufactured with 2 (or 1) copper layers. Minimum annular ring must be at 0.005” or greater. The dielectric spacing between the inner layers in 0.040” with a dielectric constant of 4.2 +/-0.2.Ħ-Layer Design: The dielectric constant is 4.2 +/-0.2. The dielectric spacing between the bottom layer and the second inner layer in 0.008” with a dielectric constant of 4.2 +/-0.2. The total board thickness will be 0.062".Ģ-Layer Design: The dielectric spacing 0.057” with a dielectric constant of 4.58 +/-0.2.Ĥ-Layer Design: The dielectric spacing between the top layer and the first inner layer is 0.008” with a dielectric constant of 4.2 +/-0.2. Thus, the total outer layer copper is between 0.0017" and 0.0021". Outer layers begin with 0.5 ounces of copper, then during through hole plating, up to 1 ounce of copper may be added to the outer layers. Inner layer copper is 1 ounce (0.0014") thick. The total board thickness will be 0.062".Ĥ-Layer/6-Layer Design: Dielectric material is FR-4 with a glass transition temperature of 180 degrees Celsius. If the board is 1 layer or does not have plated through holes, then the outer layer copper may be as low as 0.0014”, since less plating is required. As a result, very fine pitch surface mount components may not include any soldermask between the pins.Ģ-Layer Design: Dielectric material is FR-4 with a glass transition temperature of 135 degrees Celsius.
Pads on the soldermask layers are grown by 0.003” on all sides. The planes are inset 0.025” from each edge of the board. For the same reason, layers 3 and 4 should also have roughly the same distribution of copper. It’s recommended that layers 2 and 5 have roughly the same distribution of copper features to prevent warpage. Through-hole pads can either be connected to or isolated from these layers. The planes are inset 0.025” from each edge of the board.Ħ-Layer Design: The four inner layers may be solid copper planes, signal layers, or a mix of solid copper and signal traces. It’s recommended that the inner layers have roughly the same distribution of copper features to prevent warpage. There are no inner layers for this product.Ĥ-Layer Design: The two inner layers may be solid copper planes, signal layers, or a mix of solid copper and signal traces. smallest square board allowed is 0.64 x 0.64 inches).Įtching resolution is 0.005” minimum trace width, 0.005” minimum space width.Ģ-Layer Design: N/A. Total board area must be greater than 0.4 square inches (i.e. Minimum dimension in height or width is 0.35 inches. Maximum board size must be less than 22.5 inches in height and 16.5 inches in width (maximum manufacturing capability). We, at Bay Area Circuits, thought it would be helpful to share the manufacturing specifications we use to fabricate PCB orders submitted to us directly through DipTrace: